The present invention relates to transmission timing adjusting circuits and method, more particularly, to a transmission timing adjusting circuit, which comprises a phase comparison circuit for receiving a reception clock and a self-running clock and comparing the phases of the reception clock and a transmission clock, and a phase correction circuit for receiving the self-running clock and the output of the phase comparison circuit and outputting the transmission clock and a frequency division clock of the self-running clock.
In the prior art, when it is intended to use the reception clock directly as the transmission clock, it is necessary to synchronize the phase of the transmission clock for coping with phase deviation due to delay and sudden phase deviation. To this end, usually a clock is extracted from the received signal for discriminating frame synchronization, storing a digital signal and adjusting the read-out timing.
However, in RCR (Research & Development Center for Radio System, Electric Wave Development Center) -27F, which is digital system car telephone standards, the transmission clock should be controlled such that in one slot it will not be deviated by more than 1/8 symbol, and a method for doing so has been contemplated.